Core Technology of SPI Synchronous Communication

SPI (Serial Fringe Interface) transport could be a synchronous serial communication transport presented by Motorola, primarily utilized for information transmission between microcontrollers and fringe gadgets. The SPI transport is broadly connected in numerous chips, such as Motorola's M68HC08 microcontroller, TI's A-D converter TLC2543 and D-A converter TLC5615, and AD's temperature sensor AD7816. SPI transport could be a full-duplex synchronous serial transport utilized for synchronous communication between microcontrollers (MCU) and fringe gadgets.

SPI Bus Pin Functions

The SPI bus typically uses four lines: serial clock line SCK, master input/slave output data line MISO, master output/slave input data line MOSI, and the low-level active slave select line SSEL. Their specific functions are as follows:

1. MISO (Ace Input/Slave Yield): the information input line of the ace and the information yield line of the slave.

2. MOSI (Ace Output/Slave Input): the information yield line of the ace and the information input line of the slave.

3. SCK (Serial Clock): the clock flag yield line of the ace and the clock flag input line of the slave. The clock signal controls the speed of data transmission.

4. SS (Slave Select): the chip select signal of the slave.

Figure 1: Schematic diagram of SPI bus interface expansion

In SPI bus communication, there is only one master, but there can be multiple slaves. All the MOSI, MISO, and SCK lines of the slaves are connected together, and the master selects one or more slaves for communication through the chip select signal.

Clock Polarity and Phase

The data transmission of the SPI bus is controlled by the following two clock parameters:

1. CPOL (Clock Extremity Control Bit): decides the sit out of gear state level of the SCK clock line when the SPI transport is sit still. When CPOL is 0, the SCK is moo when sit out of gear; when CPOL is 1, the SCK is tall when sit still.

2. CPHA (Clock Phase Control Bit): determines the sampling position of the data on the SPI bus. When CPHA is 0, information is tested at the primary clock edge; when CPHA is 1, information is examined at the moment clock edge.

SPI Bus Timing

SPI devices can transmit and receive data on the rising or falling edge of the SCK. Information transmission can be in "most critical bit to begin with" or "slightest critical bit to begin with" arrange. For case, on the off chance that the ace gets information on the rising edge of the SCK in "most noteworthy bit to begin with" arrange, the timing is as takes after:

1. When the SS pin goes low, the slave is selected and sends the most significant bit D7 to the MISO pin.

2. At each falling edge of the SCK, the slave sends one bit of data to the MISO pin.

3. At each rising edge of the SCK, the master collects the data on the MISO pin, completing the data reception.

Figure 2: SPI bus timing diagram

Applications

SPI bus is widely used for communication between EEPROM, Flash, real-time clocks (RTC), analog-to-digital converters (ADC), network controllers, MCU, digital signal processors (DSP), and digital signal converters. The SPI system can directly interface with various standard peripheral devices and typically uses four lines for communication.

Simulating SPI Bus

For MCS-51 microcontrollers without a built-in SPI interface, the SPI transport signals and timing can be mimicked utilizing parallel I/O pins. For illustration, the P1.0, P1.1, P1.2, and P1.3 pins of the 8051 microcontroller can be utilized to reenact the MISO, MOSI, SCK, and CS pins of the SPI transport, individually.

Figure 3: Schematic chart of 8051 microcontroller pins mimicking SPI transport

Illustration Description

Figure 1 appears a schematic chart of the SPI transport interface development, with four flag lines interfacing the ace and slave gadgets. Figure 2 appears the SPI transport timing chart, and Figure 3 appears a schematic chart of 8051 microcontroller pins mimicking the SPI transport. By understanding the SPI transport, one can comprehensively get a handle on its application and execution in communication between microcontrollers and fringe gadgets.