External Bus Design of MCS-51 MCU

The control bus, data memory, I/O interface, and program memory of a microcontroller must be connected to the microcontroller's microprocessor (CPU) through a bus. The bus is a set of common signal lines that can be divided into address bus, data bus, and control bus, which connect various components of the microcontroller system.

Composition of the Control Bus

The control bus consists of ALE, PSEN, WR, and RD, each of which has the following functions:

1. ALE (Address Latch Enable Pin)

Port P0 is a time-multiplexed bus for addresses and data, and it is necessary to latch the low 8-bit address it transmits through a latch. It is crucial to drive the address latch to latch the low 8-bit address at the right time, ensuring that when the address is latched, the P0 port is transmitting the address, not the data that follows. ALE is the address latch enable pin. When the microcontroller accesses external memory and I/O ports, this pin outputs a falling edge signal before the P0 port switches from the address line to the data line. This pin can be used as the latch driving signal for the address latch to ensure that the low 8-bit address is latched.

2. PSEN (Program Store Enable Pin)

PSEN is a low-level active program store enable pin used for the extension of external program memory. When the microcontroller executes a read operation from external program memory, the PSEN pin outputs a low-level signal to gate the program memory to be accessed. This program memory access includes reading instructions and using the MOVC instruction to read data.

3. WR and RD

When working in the secondary function, the P3.6 and P3.7 pins of port P3 correspond to WR and RD, respectively. WR and RD are used for the extension of external data memory (or I/O interface) and serve as write enable and read enable signals for external data memory (or I/O interface), both being low-level active. Instructions that generate read operations from external data memory (or I/O interface) include "MOVX A,@DPTR" and "MOVX A,@Ri", while instructions that generate write operations include "MOVX@DPTR,A" and "MOVX@Ri,A". When the microcontroller reads data from external data memory (or I/O interface) and sends the data onto the external data bus, the RD pin is low, and the WR pin is high. Conversely, when writing data to external data memory (or I/O interface), the WR pin is low, and the RD pin is high. It is important to note that any two of the PSEN, WR, and RD pins will not be low at the same time, meaning that reading and writing of external data memory (or I/O interface) and reading of external program memory will not happen simultaneously.

Data Bus

The information transport could be a bidirectional transport utilized to exchange information between the microcontroller and memory units and I/O ports. The width of the information transport is by and large steady with the word length of the microcontroller CPU.

Address Bus

The address bus is used to transfer addresses of memory units or I/O ports, and the transfer direction is unidirectional, only from the microcontroller to the outside. Additionally, the number of address lines (m) determines the number of memory units and I/O ports the address bus can address. This is because each address line can transmit high and low-level signals, represented by binary numbers "1" and "0". Each logical group of binary numbers can correspond to an address. An address bus with m address lines can transmit m-bit binary numbers, for a total of 2^m addresses.

Composition of the External Bus of the MCS-51 Microcontroller

The MCS-51 microcontroller does not have a dedicated external address bus and data bus. The functions of these buses are provided by the parallel input and output ports P0 and P2 of the microcontroller. The expansion bus structure of the MCS-51 microcontroller is shown in Figure 1.

图1：The extended bus structure of MCS-51 single chip microcomputer

1. P0 Data/Address Time-Multiplexed Bus

The MCS-51 microcontroller has an 8-bit outside information transport (D7~D0) given by harbour P0. Moreover, the MCS-51 microcontroller includes a 16-bit outside address transport, with harbour P0 transmitting the moo 8 bits of the address (A7~A0). When the microcontroller accesses external extended memory and I/O interfaces, port P0 first transmits the low 8 bits of the external address and then transmits the data, meaning port P0 is a time-multiplexed bus for addresses and data. Thus, when data appears on port P0, the low 8-bit address has already disappeared from port P0. The address latch in Figure 1 can latch the low 8-bit address before it disappears and provide it to the external extended memory or I/O port.

2. P2 High 8-Bit Address Bus

When performing external expansion, port P2 is the high 8-bit address bus. Unlike port P0, port P2 only transmits addresses and is not multiplexed. The 16-bit external address line formed by port P2 and port P0 gives the MCS-51 microcontroller 2^16=65536 external addresses. The program memory and information memory units of the MCS-51 microcontroller are tended to by bytes (i.e., each byte memory unit has an address). Subsequently, the MCS-51 microcontroller can expand up to 2^16 bytes (64KB) of outside program memory and information memory.

Function of the Address Latch

The address latch in Figure 1 is used to latch the address information transmitted by port P0, triggered by the falling edge signal on the ALE pin. Therefore, the address latch in Figure 1 should be a falling-edge-triggered latch, such as the 74LS373 chip. If using a rising-edge (or high-level) triggered latch (such as the 74LS273 and 74LS377 chips), the ALE pin signal must be inverted before connecting to the latch's trigger terminal.